Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!ucsd!orion.cf.uci.edu!uci-ics!venera.isi.edu!raveling From: raveling@vaxb.isi.edu (Paul Raveling) Newsgroups: comp.sys.hp Subject: Re: Masking interrupts on 9000/360's under hp-ux Keywords: hp9000/360 interrupts masking hp-ux Message-ID: <7608@venera.isi.edu> Date: 22 Feb 89 17:38:03 GMT References: <6534@ecsvax.UUCP> Sender: news@venera.isi.edu Reply-To: raveling@isi.edu (Paul Raveling) Organization: USC-Information Sciences Institute Lines: 22 In article <6534@ecsvax.UUCP> uccjcm@ecsvax.UUCP (John McLendon) writes: > >We have an application where we need to essentially take over full control >of the hp 9000/360 for up to 100 millisecs. Caramba! That's a whale of a long time -- When we designed EPOS we specified an absolute maximum interrupt latency (~time with interrupts disabled) of 1 millisecond on a PDP-11/45 because various devices couldn't tolerate anything longer. Also, a 1 millisecond latency needed to be an infrequent case. Typical measured interrupt latency was a lot less -- we didn't have hardware that allowed accumulating a mean latency measurement, but samples suggested it would probably be between 20 & 50 microseconds when the system was busy, negligible when the system wasn't busy. ---------------- Paul Raveling Raveling@isi.edu