Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uflorida!novavax!muadib!f7.n369.z1.FIDONET.ORG!Sean.Conner
From: Sean.Conner@f7.n369.z1.FIDONET.ORG (Sean Conner)
Newsgroups: comp.sys.ibm.pc
Subject: Re: EXTENDED memory and INTERRUPTS, problems ?
Message-ID: <169.24081110@muadib.FIDONET.ORG>
Date: 26 Feb 89 02:27:00 GMT
Sender: ufgate@muadib.FIDONET.ORG (newsout1.26)
Organization: FidoNet node 1:369/7 - New Frontier's Node, Coral Springs FL
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Chris Sylvain writes:
>---> To further examine the problem, I would like to know what the 
expected
>---> frequency of interrupts is for the AT I/O chip (the 16450?) and 
the
>---> XT I/O chip (8540?) when operated at 9600 baud.
 
  Well, at 9600, you have 9,600 bits of information per second, or one 
bit per 104 uSeconds (micro seconds).  Since there's 10 bits sent per 
byte (Start, 8 data (7 data, 1 parity) and Stop), you have (assuming 
that data is comming is ASAP) a Received-Data interrupt every 1.04 
mSeconds (milliseconds).
  The frequency if interrupts is independant of the I/O chip (as it 
seems to me).  Hope that helps somewhat.
  -Sean