Path: utzoo!utgpu!attcan!uunet!lll-winken!ames!elroy!cit-vax!wetter
From: wetter@cit-vax.Caltech.Edu (Pierce T. Wetter)
Newsgroups: comp.sys.mac
Subject: Pierce Explains RISC. was new mac rumors
Message-ID: <9770@cit-vax.Caltech.Edu>
Date: 25 Feb 89 21:33:19 GMT
References: <70755@ti-csl.csc.ti.com>
Organization: California Institute of Technology
Lines: 29

> 
> This is very interesting.  I don't have the strongest background in
> hardware architecture, but, could you please explain how a processor
> could be optimized for a specific high level language?
> 
     The speed of a mircoprocessor is somewhat proportional to the number
of instructions it has to implement. For instance the 6502 can do every 
instruction in one clock cycle, while the 68000 can take up to 70.

     However, most HLL use 20% of the instructions 80% of the time. (80-20)
rule. If we optimize those instructions, and allow the others to be
constructed out of the major instuctions we can get a significant speed increase
  The other thing that most HLL need is lots and lots of registers. The
68000 has 16, but 1 is a stack pointer(a7), 1 points to the global area(a5), and
another points to the local area(a6), and one is used to return function values
(d0), leaving only 5 address and 7 data registers available. Some RISC chips
on the other hand have up to 25 registers, a 256byte data cache, and a program
cache. Some even have registers big enough to hold an entire 96-bit floating
point number.

   That's the basic gist of how Reduced Instruction Set CPU's if you want more
info you can get the data sheets for the 88000, or one of the other new risc
chips and they'll go into a lot more detail.
Pierce
-- 
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