Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cornell!biar!trebor
From: trebor@biar.UUCP (Robert J Woodhead)
Newsgroups: comp.sys.mac
Subject: Re: Pierce Explains RISC. was new mac rumors
Message-ID: <165@biar.UUCP>
Date: 27 Feb 89 14:42:28 GMT
References: <161@biar.UUCP> <9795@cit-vax.Caltech.Edu>
Reply-To: trebor@biar.UUCP (Robert J Woodhead)
Organization: Biar Games, Inc.
Lines: 21

In article <9795@cit-vax.Caltech.Edu> wetter@cit-vax.Caltech.Edu (Pierce T. Wetter) writes:
>    Ooops, sorry. I meant many 6502 instructions take ~ 1 cycle. I obviously
>didn't expect a multiply to run in one cycle.

The 6502 does not have a multiply instruction.  As I remember it (I haven't
looked up the instruction timings in years) each cycle on a 6502 is a
complete bus operation).  Thus, the only instructions
that are 1 cycle long are those without memory or immediate operands, such as
TAX or CLC.  This is a very small number of instructions.

The 6502 was, for it's time, an extremely elegant architecture.  After all,
the chip really has 128 16 bit registers; they just happen to be in the
first 256 bytes of ram.  However, it was designed before, and does not even
approach, the RISC concept of 1 instruction = 1 cycle.

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