Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!ie.ucd.eurokom!Trevor_Carden_THORN_EMI_CRL From: Trevor_Carden_THORN_EMI_CRL@ie.ucd.eurokom Newsgroups: comp.sys.transputer Subject: Re: C004 Dynamic Switching Message-ID: <8902232013.54276@eurokom.ie> Date: 24 Feb 89 04:13:00 GMT Sender: daemon@ucbvax.BERKELEY.EDU Organization: The Internet Lines: 50 Moshe Braner comments: >One disadvantage of using a 2-layer C004 switching network is that, >going through 3 C004's in a row, the data transfer rate on the link >is reduced by a half ... >Is there any solution for the layered approach (e.g. faster switch-chips)? The C004 provides link switching and also clock resynchronization to avoid signal skews adding up from one switch to the next. It is this resynchronization that causes the delay of about 1.75 bit periods when passing through each C004 in each direction. It would be very difficult to reduce this in a new C004 design while still providing resynchronization that is able to tolerate slightly different clock rates at each end of a link. In the ESPRIT Supernode project in which the Inmos T800 and the Parsys SN1000 series were developed, much attention was paid to providing a two layer switch architecture that would not impose significant bandwidth restrictions on the link traffic. The overlapped acknowledge of the T800 links was introduced to allow at least one clock resynchronization to occur along a link connection without affecting bandwidth. In addition, no clock resynchronization is used in the 72 wide Supernode link switch, so only a small propagation delay of a fraction of a bit period occurs. The second layer switch for making Inter-node connections from one Supernode to another does use C004 switches, and hence preserves signal quality. Using this combination, a two layer switch can be built that does not affect link bandwidth and allows simple configuration of any transputer network. Large systems of over 1000 transputers can be supported in this way, though the physical size of such a system makes additional buffering and resynchronization necessary for Inter-node connections. These extra buffers make the Inter-node link delay similar to that in a system using two layers of C004 switches. However, a wide switch at the Supernode level was chosen so that each Supernode contains as many transputers as possible. The number of link connections that have to pass through the Inter-node switch is therefore minimized, allowing most links to operate at full bandwidth. ----------------------------------------------------------------------- Trevor Carden (01 or +44 1) 848 6504 Parsys Ltd., THORN EMI CRL Dawley Road, Hayes, Middlesex, UB3 1HH, England Trevor_Carden_THORN_EMI_CRL%eurokom.ucd.irl@euroies.uucp