Xref: utzoo comp.arch:8671 comp.periphs:1596 Path: utzoo!yunexus!torsqnt!dptcdc!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!bloom-beacon!apple!vsi1!wyse!mips!randy From: randy@mips.COM (Randy Scofield) Newsgroups: comp.arch,comp.periphs Subject: HSC Keywords: Want info Message-ID: <14875@giant.mips.COM> Date: 8 Mar 89 16:41:37 GMT Article-I.D.: giant.14875 Lines: 16 Hi, Is anyone out there designing peripherals to talk to HSC? HSC is a proposed ANSI standard (X3T9.3). For those that are unfamiliar: HSC (High Speed Communications) is a point to point data channel that has a 100Mbyte/S or 200Mbyte/S transfer rate depending on whether you use the 32 or 64 bit data width. It uses one ecl 100 pin differential D-shell connector per 32 bits of width. HSC is unidirectional, and 2 channels must be used to make a full duplex connection. HSC is based on a 25MHZ (40ns) clock, and transfers one 64/32 bit word per clock once a connection is established. HSC is for data only, and there is no address lines. Thanks, Randy Scofield -- - Randy Scofield (disclaimer:**I speak for me, etc) UUCP: {decvax,ucbvax,ihnp4,hplabs}!decwrl!mips!randy USPS: MIPS Computer Systems, 930 Arques, Sunnyvale, CA 94086, (408) 720-1700