Xref: utzoo comp.arch:8641 comp.sys.hp:1667
Path: utzoo!utgpu!watmath!cantuar!greg
From: greg@cantuar.UUCP (G. Ewing)
Newsgroups: comp.arch,comp.sys.hp
Subject: Was *this* the first RISC chip?
Keywords: Hewlett-Packard, microprocessor, RISC
Message-ID: <1068@cantuar.UUCP>
Date: 7 Mar 89 02:32:12 GMT
Reply-To: greg@cantuar.UUCP (G. Ewing)
Organization: University of Canterbury, Christchurch, New Zealand
Lines: 25

During a recent fit of idle curiosity, I came across some articles
describing the microprocessor used in many of HP's handheld
calculators from the HP-35 on.

It occurred to me that the design is actually quite RISCy in some
ways.  All instructions are the same length (10 bits) and execute
(I think) in one cycle (if you count a 56-bit serial shift as a
"cycle"). All arithmetic/logic operations are done in registers.

Other interesting features include a (very!) split I/D space (10 bit
ROM for instructions, 56-bit registers and data memory) and an
instruction set optimised for BCD arithmetic on various fields
of decimal floating-point numbers (mantisssa, sign, etc.)

Anyway, I think it's kind of cute. Does anyone know where I can
find out more about it? Ideally I'd like enough info to write a
simulator for it (okay, so I'm wierd). The articles I have (from
the HP Journal) don't go into much detail.

Any help appreciated,

Greg Ewing				Internet: greg@cantuar.uucp
Spearnet: greg@nz.ac.cantuar		Telecom: +64 3 667 001 x8357
UUCP:	  ...!{watmath,munnari,mcvax,vuwcomp}!cantuar!greg
Post:	  Computer Science Dept, Univ. of Canterbury, Christchurch, New Zealand
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