Xref: utzoo comp.arch:8693 comp.sys.hp:1677
Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!decwrl!sun!pitstop!sundc!seismo!uunet!mcvax!ukc!etive!hwcs!zen!graeme
From: graeme@zen.UUCP (Graeme Cawsey)
Newsgroups: comp.arch,comp.sys.hp
Subject: Re: Was *this* the first RISC chip?
Keywords: Hewlett-Packard, microprocessor, RISC
Message-ID: <1537@zen.UUCP>
Date: 8 Mar 89 14:49:21 GMT
References: <1068@cantuar.UUCP>
Reply-To: graeme@zen.UUCP (Graeme Cawsey)
Organization: Zengrange Limited, Leeds, England
Lines: 15

In article <1068@cantuar.UUCP> greg@cantuar.UUCP (G. Ewing) writes:
>
>It occurred to me that the design is actually quite RISCy in some
>ways.  All instructions are the same length (10 bits) and execute
>(I think) in one cycle (if you count a 56-bit serial shift as a
>"cycle"). All arithmetic/logic operations are done in registers.

On the Nut series of CPUs (HP-41, HP-1x), and I presume on the earlier
versions, not all instruction are one word in length.  Load immediate (LDI),
power off (POWOFF) and absolute branch (CGO & NCGO) and calls (CXQ & NCXQ)
are all two word instructions taking two cycles and the ROM fetch instruction
(RDROM) is a one word instruction that takes two cycles.

Graeme Cawsey (graeme@zen.co.uk)
Zengrange Ltd., Greenfield Rd., Leeds, England, LS9 8DB. Tel : +44 532 489048