Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!hplabs!hpda!hpcupt1!hprnd!clw
From: clw@hprnd.HP.COM (Carl Wuebker)
Newsgroups: comp.sys.hp
Subject: Re: HP 9825A (was Was *this* the first RISC chip?)
Message-ID: <2630003@hprnd.HP.COM>
Date: 9 Mar 89 16:54:04 GMT
References: <16274@mimsy.UUCP>
Organization: HP Roseville Networks Division
Lines: 26


     In response to the title, the 9825A processor was something called the 
BPC hybrid -- composed of 3 chips mounted on a ceramic? plate.  The chips 
were the BPC (Binary? Processor Chip), the IOC (I/O chip) and the EMC (Extended
Math Chip).  The 3 chips cooperated as an instruction slice computer -- the BPC
(if I remember) did the instruction fetch and all integer instructions, the IOC
did the I/O operations and the EMC did BCD math (I'm not sure if it did X or /).

     Anyway, while the BPC might have been considered a RISC chip (it used a
minor variant of the HP2100 (later HP1000) instruction set), to my knowlege
it was never used without either the EMC or IOC in a product.   The 9845A,
the next model, was a 'dual-processor' computer composed of a Peripheral 
Processing Unit (PPU, it was a BPC and an IOC) and the Language Processing
Unit (LPU, it had a BPC and an EMC).  4-bit processors (4004, 4040) had been
out for quite a while (1971), 8 bit processors were out but new (1975 or so);
the 9825A may have been the 1st product to use a 16-bit chipset commercially.

     We had a neat history string in the HP notesgroups about a year ago.  The
9830A, predecessor to the 9825A, ran a similar instruction set -- implemented
as a 16-wide bit serial processor which ran entirely out of the microcode in
a 256-byte ROM!  I saw the flowchart for that ROM's state machine once -- 
it was incredible what those engineers were able to do with so little!

Thanks,
   Carl "it even used a 6MHz +/-10% FM clock!" Wuebker 
   * clw@hprnd * HP Roseville Networks Division * (916) 785-4296 *