Xref: utzoo comp.sys.intel:724 comp.sys.ibm.pc:25631
Path: utzoo!utgpu!watmath!iuvax!bobmon
From: bobmon@iuvax.cs.indiana.edu (RAMontante)
Newsgroups: comp.sys.intel,comp.sys.ibm.pc
Subject: Re: New Intel Chip
Summary: no it isn't the '486
Message-ID: <18206@iuvax.cs.indiana.edu>
Date: 4 Mar 89 05:59:22 GMT
Reply-To: bobmon@iuvax.cs.indiana.edu (RAMontante)
Organization: malkaryotic
Lines: 58

-Is this the 80486 we have all been waiting for??

The comp.arch newsgroup has been all agog about this.  It was apparently
known as the N-10, is now called the i860.  In scanning Intel's "official"
posting about it, I see little to think is is related to the misbegotten
80x86 line (aHEM).  For example, it includes 32 32-bit general-purpose
registers.  As I understand it, much of its performance derives from the
ability to execute one integer operation and two floating-point operations
simultaneously, with "all" instructions (be they single-op or multi-op)
taking 3 clock cycles.  (Don't quote me.)  A few excerpts follow (see
comp.arch for the full 125-line Intel statement) (spelling errors in the
following were in the original posting too):
	____________

The following information is taken from the i860 TM 64-Bit Microprocessor
data sheet order number 240296-001.	[ ... ]

			i860 64-bit Microprocessor

Highlights:

Parallel Architecture:  3 instructions Clock
	- one integer or control instruction
	- up to to Floating Point Instructions

High Performance Design
	- 33.3/40 MHz Clock Rate
	- 80 MFLOP Peak Single Precision MFLOPs
	- 60 MFLOP Peak Double Precision MFLOPs
	- 64-bit External Data Bus
	- 64-bit Internal Instruction Cache Bus
	- 128-bit Internal Data Cache Bus	

Measured Performance with Current Compilers
	- 24 Megawhetsones (40 MHz)
	- 83K Dhrystones (40 MHz)

Highly Integrated
	- 32/64-bit Pipelined Floating-Point Adder and Multipler
	- 32-bit Integer and Control Unit
	- 64-Bit 3-D Graphics Unit
	- Paging Unitg with TLB
	- 4K Byte Instruction Cache
	- 8K Byte Data Cache

[ technical descriptions deleted ...
  There is a meta-interesting line: ]

{Editors note the i860 CPU's paging mechanism is the same
as the 386 CPU.}

So I guess it is partially misbegotten :-)  I can't tell if this is a
comment by the Intel poster, a comment by someone who edited the posting, or
an instruction to magazine editors who might use this posting...
-- 
Those who do not understand MSDOS are  | Bob Montante (bobmon@cs.indiana.edu)
condemned to write glowingly of it in  | Computer Science Department
slick, short-lived magazines.          | Indiana University, Bloomington IN