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From: mark@mips.COM (Mark G. Johnson)
Newsgroups: comp.arch,comp.sys.intel
Subject: Re: i860 CPU information (Previously: N10 Info)
Message-ID: <14616@obiwan.mips.COM>
Date: 4 Mar 89 16:21:33 GMT
References: <208@intelca.intel.com>
Reply-To: mark@mips.COM (Mark G. Johnson)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 23

Thanks for Clif Purkiser for an informative posting! <208@intelca.intel.com>
did raise a question, though:

>Highly Integrated
>	- 32/64-bit Pipelined Floating-Point Adder and Multipler
>	- 32-bit Integer and Control Unit
>	- 64-Bit 3-D Graphics Unit
>	- Paging Unitg with TLB
>	- 4K Byte Instruction Cache
>	- 8K Byte Data Cache


Perhaps the list above is simply incomplete; by an omission it leads to
speculations like:
	1.  Is there a Floating-Point Divider in hardware?
	2.  Are there Floating-Point Divide instructions (IEEE 32b & 64b)
		in the 80860 architecture?
	3.  How many clocks does it take to do an IEEE 32b divide?  64b?
Thanks.
-- 
 -- Mark Johnson	
 	MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
	...!decwrl!mips!mark	(408) 991-0208