Xref: utzoo comp.arch:8664 comp.sys.intel:741
Newsgroups: comp.arch,comp.sys.intel
Path: utzoo!henry
From: henry@utzoo.uucp (Henry Spencer)
Subject: Re: i860 overview (long)
Message-ID: <1989Mar8.183152.2057@utzoo.uucp>
Organization: U of Toronto Zoology
References: <807@microsoft.UUCP> <92634@sun.uucp> <13322@steinmetz.ge.com>
Date: Wed, 8 Mar 89 18:31:52 GMT

In article <13322@steinmetz.ge.com> davidsen@crdos1.UUCP (bill davidsen) writes:
>One problem with any chip which requires alligned data is that
>performance suffers when addressing bytes, to the point that a program
>may become impractical. One of the people here checked his Sun-30
>(68020) against his Sun-4 (SPARC). The three ran troff about 5x faster.

This is curious, since troff does little byte addressing.  Doubly so
since the SPARC does have byte addressing and byte-access instructions.

More generally, are you not confusing alignment with accessing?  It is
quite possible to require aligned data (e.g. 32-bit quantities on 32-bit
boundaries) while still having efficient byte addressing and accessing.
-- 
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