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From: jeff@Alliant.COM (Jeff Collins)
Newsgroups: comp.arch,comp.sys.intel
Subject: Re: i860 overview (long)
Message-ID: <3019@alliant.Alliant.COM>
Date: 6 Mar 89 16:43:42 GMT
References: <807@microsoft.UUCP>
Reply-To: jeff@alliant.Alliant.COM (Jeff Collins)
Organization: Technology Partners, Inc.
Lines: 28

In article <807@microsoft.UUCP> jangr@microsoft.UUCP (Jan Gray) writes:
>
>				i860 Overview
>
> <deleted lots of interesting and useful data on the i860>
>Caches
>
>* 8K data cache, virtual addressed, write-back, two-way "set associative",
>  2x128 lines of 32 bytes
>* Flush instruction forces a dirty data cache line (32 bytes) back to memory.
>  Intel supplies suggested code to flush entire data cache.
>* Storing to dirbase register with ITI bit set invalidates TLB and instruction
>  caches; must flush data cache first!  [Remember, the data cache is virtually
>  addressed.]

	Coming from a multiprocessor background, I personally judge the
desirability of a chip by the ability to put it into an MP architecture.  One
of the most important features necessary for this is the ability to invalidate
any internal data caches from external hardware.  The discussions that I have
seen on the i860 have not made it clear whether this possible or not.   Given
that the internal data cache is a virtual, write-back, two-way set
associative, I would guess this is not possible.  Does any one know for
certain?

	If it is impossible the invalidate the cache from external logic, the
next question is how does the chip perform with the internal data cache
disabled?  Also, is there any way to disable the cache without using the PTE
bit?