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From: seanf@sco.COM (Sean Fagan)
Newsgroups: comp.arch,comp.sys.intel
Subject: Re: i860 CPU information (Previously: N10 Info)
Message-ID: <2393@scolex.sco.COM>
Date: 6 Mar 89 07:06:50 GMT
References: <208@intelca.intel.com> <14616@obiwan.mips.COM>
Reply-To: seanf@scolex.UUCP (Sean Fagan)
Organization: The Santa Cruz Operation, Inc.
Lines: 25

In article <14616@obiwan.mips.COM> mark@mips.COM (Mark G. Johnson) writes:
>Perhaps the list above is simply incomplete; by an omission it leads to
>speculations like:
>	1.  Is there a Floating-Point Divider in hardware?

No.

>	2.  Are there Floating-Point Divide instructions (IEEE 32b & 64b)
>		in the 80860 architecture?

No.

>	3.  How many clocks does it take to do an IEEE 32b divide?  64b?

Depends.  I think it might be somewhere around 30-40 (40-50?), but I'm not
sure.  It doesn't have divide in hardware; what it has is reciporacal
approximations (1.0/x), so you do that (plus a little bit to get rid of the
errors), then multiply.

Kinda like a Cray, right? 8-)

-- 
Sean Eric Fagan  | "What the caterpillar calls the end of the world,
seanf@sco.UUCP   |  the master calls a butterfly."  -- Richard Bach
(408) 458-1422   | Any opinions expressed are my own, not my employers'.