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Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!oliveb!apple!vsi1!zorch!tolerant!rob
From: rob@tolerant.UUCP (Rob Kleinschmidt)
Newsgroups: comp.arch,comp.sys.intel
Subject: Re: i860 overview (long)
Summary: alignment vs. cache
Message-ID: <4014@tolerant.UUCP>
Date: 10 Mar 89 02:11:08 GMT
References: <807@microsoft.UUCP> <92634@sun.uucp> <13322@steinmetz.ge.com> <12000@haddock.ima.isc.com>
Organization: Tolerant Systems Inc., San Jose California
Lines: 13

In article <12000@haddock.ima.isc.com>, suitti@haddock.ima.isc.com (Stephen Uitti) writes:
> In article <1133@auspex.UUCP> guy@auspex.UUCP (Guy Harris) writes:
> 
> > [attempted explanations]
> >This leaves 1) or 2); is there one I missed?
> 
For the sake of argument...	Under some very wierd circumstances, one
might be able to demonstrate better cache utilization on a byte aligned vs.
"naturally" aligned machine. Assuming multi-byte cache lines, one could
argue some small improvement because of the lack of padding bytes within
structures etc. I don't believe this for a minute, and assume that any
small gain made would be offset by the extra cpu access cycles, but it
seemed like a thought worth mentioning.