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From: nagel@blanche.ics.uci.edu (Mark Nagel)
Newsgroups: comp.arch
Subject: MIPS R2000 questions
Message-ID: <9060@paris.ics.uci.edu>
Date: 12 Mar 89 06:20:21 GMT
Sender: news@paris.ics.uci.edu
Reply-To: nagel@ics.uci.edu (Mark Nagel)
Organization: University of California, Irvine - Dept of ICS
Lines: 27

Hi there.  I'm in need of some answers to some questions I have about
the MIPS R2000 processor.  Specifically, I'm implementing a simulation
of the MIPS for an academic project and I've run into the limitations
of using [Kane] as a reference for this simulation.

My questions pertain to the R2000 pipeline -- what happens to it in
the event of a cache miss?  Among other things, how many cycles are
used in fetching a line into the cache in some typical machine X?  How
does the delayed load work properly in the event of a cache miss?
From the information in the book and what little I can surmise from
life in general, if a cache miss occurred and it, say, doubled the
length of the MEM pipeline stage (is that what happens?) then the
loaded value can no longer be available to the ALU stage of the
instruction after the load delay slot.  This must be incorrect since
there are real live machines out there that must have cache misses :-)
[Kane] implies that there is no fancy interlocking and delaying of the
pipeline, etc., but it also implies there will never be a cache miss
(or at least it never addresses the problem other than mentioning the
D-cache miss status bit).

Could someone please set me straight on this?  I'd very much
appreciate it.

Mark Nagel @ UC Irvine, Department of Information and Computer Science
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