Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!bloom-beacon!apple!vsi1!wyse!mips!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.arch Subject: Re: i860 CPU information Keywords: i860 N10 Message-ID: <15040@winchester.mips.COM> Date: 10 Mar 89 17:56:03 GMT References: <1895@oakhill.UUCP> <21570@shemp.CS.UCLA.EDU> Reply-To: mash@mips.COM (John Mashey) Distribution: usa Organization: MIPS Computer Systems, Sunnyvale, CA Lines: 22 In article <21570@shemp.CS.UCLA.EDU> marc@cs.ucla.edu (Marc Tremblay) writes: >For other systems, such as the MIPS M/2000 processor board, or >the Tadpole VME board based on the 88000, cache sizes for both >instructions and data are the same. >Although the sizes of the caches for these system are independent, >none of them have the "opposite" (having a larger instruction cache). >Last time I heard, they intended to run UNIX on these machines :-) . >Based on the choices made at MIPS (2 64k caches), they probably >obtained simulations that show that performance/cost was optimized >for equal size caches. The MIPS M/500 uses 16K I + 8K D cache, having grown up from the 8KI + 8K D predecessor (about 1 BVUP difference by doubling the I-cache). No, the reason was to get the largest caches that were electrically reasonable. We'd lessen the D-cache first.... -- -john mashey DISCLAIMER: UUCP: {ames,decwrl,prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086