Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uflorida!haven!rutgers!ucla-cs!loving
From: loving@lanai.cs.ucla.edu (Mike Loving)
Newsgroups: comp.arch
Subject: Re: So, can you really fab 10**6 transistors now?
Message-ID: <21668@shemp.CS.UCLA.EDU>
Date: 13 Mar 89 22:01:10 GMT
References: <7392@polya.Stanford.EDU> <62230001@hpl-opus.HP.COM> <1989Mar13.165931.22528@utzoo.uucp>
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Reply-To: loving@cs.ucla.edu (Mike Loving)
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In article <1989Mar13.165931.22528@utzoo.uucp> henry@utzoo.uucp (Henry Spencer) writes:
>In article <62230001@hpl-opus.HP.COM> poulton@hpl-opus.HP.COM (Ken Poulton) writes:
>>... In *1982*, HP presented (at ISSCC) a 32bit CPU with 
>>450K transistors.  It was fabbed in a 1.3um NMOS process.  Yield was
>>microscopic at the time of the paper, but soon came up...
>
>I seem to recall a non-HP assessment somewhere which said something like:
>"The difficulty of getting good results from this self-aligning process
>is demonstrated by the fact that it hasn't been used for anything else
>since."
>-- 

au contraire   the exact same process was used for fabbing 4 or 5 other
chips in that same machine and a slightly improved version of it was/is used
to fabricate the chips for Spectrum (HP Precision Architecture - RISC)

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Mike Loving          loving@lanai.cs.ucla.edu
                     . . . {hplabs,ucbvax,uunet}!cs.ucla.edu!loving
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