Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!bloom-beacon!apple!voder!pyramid!prls!philabs!linus!alliant!jeff
From: jeff@Alliant.COM (Jeff Collins)
Newsgroups: comp.arch
Subject: Re: i860 CPU information
Keywords: i860 N10
Message-ID: <3024@alliant.Alliant.COM>
Date: 10 Mar 89 20:17:37 GMT
References: <1895@oakhill.UUCP> <21570@shemp.CS.UCLA.EDU>
Reply-To: jeff@alliant.Alliant.COM (Jeff Collins)
Distribution: usa
Organization: Technology Partners, Inc.
Lines: 15

In article <21570@shemp.CS.UCLA.EDU> marc@cs.ucla.edu (Marc Tremblay) writes:
:In article <1895@oakhill.UUCP> tomj@oakhill.UUCP (Tom Johnson) writes:
::4)  Still on the subject of the caches:  There is no way to externally
::    invalidate cache lines.  This makes the part virtually unusable in multi-
::    processing configurations, since cache coherency cannot be maintained.
:
:Invalidating cache lines externally is not an absolute requirement for 
:using caches in a multi-processor environment. 
:There are policies that do not require this feature at all.

	Which policies are these?  How does one share memory in a
	multiprocessor when you can't have external bus watchers?
	Actually never mind that, how do you switch a process from one
	processor to another (I don't count flushing the D-cache on
	each context switch as a viable answer)?