Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uflorida!haven!adm!husc6!hscfvax!pavlov
From: pavlov@hscfvax.harvard.edu (G.Pavlov)
Newsgroups: comp.arch
Subject: Re: So, can you really fab 10**6 transistors now?
Message-ID: <744@hscfvax.harvard.edu>
Date: 14 Mar 89 14:22:18 GMT
References: <7392@polya.Stanford.EDU> <62230001@hpl-opus.HP.COM> <1989Mar13.165931.22528@utzoo.uucp>
Organization: Health Sciences Computing Facility, Harvard University
Lines: 18

In article <1989Mar13.165931.22528@utzoo.uucp>, henry@utzoo.uucp (Henry Spencer) writes:
> In article <62230001@hpl-opus.HP.COM> poulton@hpl-opus.HP.COM (Ken Poulton) writes:
> >... In *1982*, HP presented (at ISSCC) a 32bit CPU with 
> >450K transistors.  It was fabbed in a 1.3um NMOS process.  Yield was
> >microscopic at the time of the paper, but soon came up...
> 
> I seem to recall a non-HP assessment somewhere which said something like:
> "The difficulty of getting good results from this self-aligning process
> is demonstrated by the fact that it hasn't been used for anything else
> since."
> -- 
  Well, granted that it was nowhere near 450k's worth of cpu.  But the HP9000/
  500 did use several other chips (i/o processor, for one) that were in the
  same architectural family and using the same process.  And a similar 
  process was applied to the Spectrum (at least the first generation).


  greg pavlov, fstrf, amherst, ny