Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!bloom-beacon!oberon!ucla-cs!marc
From: marc@oahu.cs.ucla.edu (Marc Tremblay)
Newsgroups: comp.arch
Subject: Re: i860 CPU information
Keywords: i860 N10
Message-ID: <21784@shemp.CS.UCLA.EDU>
Date: 15 Mar 89 17:57:50 GMT
References: <1895@oakhill.UUCP> <21570@shemp.CS.UCLA.EDU> <3024@alliant.Alliant.COM>
Sender: news@CS.UCLA.EDU
Reply-To: marc@cs.ucla.edu (Marc Tremblay)
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Organization: UCLA Computer Science Department
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In article <3024@alliant.Alliant.COM> jeff@alliant.Alliant.COM (Jeff Collins) writes:
>In article <21570@shemp.CS.UCLA.EDU> marc@cs.ucla.edu (Marc Tremblay) writes:
>:Invalidating cache lines externally is not an absolute requirement for 
>:using caches in a multi-processor environment. 
>:There are policies that do not require this feature at all.
>
>	Which policies are these?  How does one share memory in a
>	multiprocessor when you can't have external bus watchers?
>	Actually never mind that, how do you switch a process from one
>	processor to another (I don't count flushing the D-cache on
>	each context switch as a viable answer)?

1) As mentioned in another article making sharable pages uncachable
   can be a viable answer for various configurations. Remember not
   everything is bus-based, (i.g. interconnection networks),
   so a broadcasts may not be allowed.

2) Directory-based cache coherency scheme: several papers have been
   published about this method. One of them is:

      "A New Solution to Coherence Problems in Multicache Systems"
      L.M. Censier and P. Feautrier,
      IEEE Transactions on Computers, TC-12, Dec. 1978, pp. 1112-1118.

   The basic trick consists of appending a small vector of bits to
   each main memory block. The vector needs to be N+1 bits long where
   N is the number of processors in the system. One bit/cache is
   necessary to indicate the presence or absence of the block in
   each cache and an extra bit indicates if the block has been
   modified or not. Reads, Writes, Misses, are explained in the paper.

   A "cheaper" solution has been proposed in:

      "An Economical Solution to the Cache Coherence Problem"
      James Archibald and Jean Loup Baer, 
      11th Annual Symposium on Computer Architecture,
      June 1984, Ann Arbor MI, pp. 355-371

   In this paper the overhead of adding a vector to each memory
   block is reduced to 2 bits/block.

Bus watchers are nice but are not an absolute necessity for
implementing efficient multiprocessor systems.

					Marc Tremblay
					marc@CS.UCLA.EDU
					Computer Science Department, UCLA