Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!iuvax!rutgers!apple!vsi1!wyse!mips!mash
From: mash@mips.COM (John Mashey)
Newsgroups: comp.arch
Subject: Re: i860 CPU information
Keywords: i860 N10
Message-ID: <15340@winchester.mips.COM>
Date: 16 Mar 89 02:58:46 GMT
References: <1895@oakhill.UUCP> <21570@shemp.CS.UCLA.EDU> <3024@alliant.Alliant.COM> <15213@winchester.mips.COM> <706@m3.mfci.UUCP> <21795@shemp.CS.UCLA.EDU>
Reply-To: mash@mips.COM (John Mashey)
Distribution: usa
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 29

In article <21795@shemp.CS.UCLA.EDU> loving@cs.ucla.edu (Mike Loving) writes:
>In article <15213@winchester.mips.COM> mash@mips.COM (John Mashey) writes:

>>As I posted in <15016@winchester>, you have to flush the caches
>>on context-switch in a single CPU, much less a multiprocessor.
>
>
>A popular misconception.  It is NOT necessary to flush the cache on a context
>switch.  If your cache is physically addressed and you do not include PIDs in
>the tags, then yes you do have to.  An example circumventing this is the new
>HP machines which use a virtually addressed (no address xlat delay) cache and
>do not flush the cache on context switches.

Apparently <15016@winchester> got lost, or people 'n'd it.

This is NOT a populatr misconception.  If you have a "simple"
virtual-addressed/virtual-tagged cache, i.e., as in the i860, with
neither pids/asids, nor the (more complex) segment-style scheme of HP PA,
then you will flush the caches on context switches, and you might do it
more often, depending on the TLB/cache interactions, and how tricky the
OS wants to get in deferring flushes.

Physically-addressed caches don't need any flushes on context-switch
or re-maps; you must have meant "If your cache is virtually addressed"
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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