Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!cs.utexas.edu!loyola!ross!doug
From: doug@ross.UUCP (doug carmean)
Newsgroups: comp.arch
Subject: Re: i860 information
Message-ID: <225@ross.UUCP>
Date: 16 Mar 89 18:53:29 GMT
Reply-To: doug@ross.UUCP (doug carmean)
Organization: ROSS Technology. Austin, TX
Lines: 20

.
.<21984@lll-winken.LLNL.GOV> brooks@maddog.llnl.gov (Eugene Brooks) Writes:
>Even explicit cache flushing for the communication could be used, but
>the cost of doing this is horrible context switching overhead for cache
>sizes large enough to be useful. Your notion of including a context descriptor
>in the cache line is useful for this, but one will still pay a cost when
>you need to clear the cache of a specific descriptor upon process death.
>At least, it is a better situation than having to clear the cache on every
>context switch.
.
A cache that stores context numbers does not need to flush an entry upon
the death of a given context.  The cache will flush the entry when that 
particular context number is used again.    A cache controller in this
type of system will include a function to flush based on context number 
only.  Flushing based purely on context will save the processor from having
to flush the entire cache when a context is reused.
-- 
-doug carmean
-ROSS Technology, 7748 Hwy 290 West Suite 400, Austin, TX 78736
-ross!doug@cs.utexas.edu