Path: utzoo!attcan!uunet!husc6!mailrus!csd4.milw.wisc.edu!uxc!uxc.cso.uiuc.edu!mcdurb!aglew
From: aglew@mcdurb.Urbana.Gould.COM
Newsgroups: comp.arch
Subject: Re: So, can you really fab 10**6 transi
Message-ID: <28200289@mcdurb>
Date: 17 Mar 89 14:34:00 GMT
References: <7392@polya.Stanford.EDU>
Lines: 12
Nf-ID: #R:polya.Stanford.EDU:7392:mcdurb:28200289:000:595
Nf-From: mcdurb.Urbana.Gould.COM!aglew    Mar 17 08:34:00 1989


>In *1982*, HP presented (at ISSCC) a 32bit CPU with 
>450K transistors.  It was fabbed in a 1.3um NMOS process.  Yield was
>microscopic at the time of the paper, but soon came up to quite
>good levels.  It was the CPU for the HP 9000 series 500, which
>I think we still sell.

I remember HP engineers coming round and giving our EE Department
blurbs on the chip, saying things like "a complicated instruction
set facilitates HLL programming and promotes performance".
RISC was relatively new, but I almost choked. I remember thinking
"I wish I had that many devices for a *good* architecture".