Path: utzoo!attcan!uunet!lll-winken!ames!mailrus!csd4.milw.wisc.edu!uxc!uxc.cso.uiuc.edu!mcdurb!aglew
From: aglew@mcdurb.Urbana.Gould.COM
Newsgroups: comp.arch
Subject: Re: Intel/MIPS Dhrystone ratio
Message-ID: <28200290@mcdurb>
Date: 17 Mar 89 14:52:00 GMT
References: <1552@vicom.COM>
Lines: 19
Nf-ID: #R:vicom.COM:1552:mcdurb:28200290:000:849
Nf-From: mcdurb.Urbana.Gould.COM!aglew    Mar 17 08:52:00 1989


>Elegant exception handling?
>Frankly, the relatively simple exception handling on many of the current
>RISCS is much more elegant than all the garbage that showed up on the
>CISC machines.

Bravo!
Who needs vectored interrupts? 
How often does your device know better where to interrupt to than you do?

But (a bit more) seriously:
how can interrupt (not exception) handling be made better/worse?
As an erstwhile systems programmer in a real-time OS, I know that we often
wished that interrupts could be treated exactly like processes,
going through the same priority or deadline driven scheduler.
Yet applying RISC principles to the hardware that would be needed to do
something like this, I often arrive at the conclusion that a 
simple single entry point first level handler is all that is appropriate.
Everything else seems to need sequencing.