Path: utzoo!attcan!uunet!lll-winken!ames!mailrus!cornell!uw-beaver!uw-june!robertb
From: robertb@june.cs.washington.edu (Robert Bedichek)
Newsgroups: comp.arch
Subject: Re: i860 CPU information
Keywords: i860 N10
Message-ID: <7630@june.cs.washington.edu>
Date: 18 Mar 89 18:06:28 GMT
References: <1895@oakhill.UUCP> <21570@shemp.CS.UCLA.EDU> <3024@alliant.Alliant.COM> <15213@winchester.mips.COM> <706@m3.mfci.UUCP> <3040@alliant.Alliant.COM>
Reply-To: robertb@uw-june.UUCP (Robert Bedichek)
Organization: U of Washington, Computer Science, Seattle
Lines: 39

In article <3040@alliant.Alliant.COM> 
  jeff@alliant.Alliant.COM (Jeff Collins) writes:
>	Yep, that is the way most people do it, but my understanding
>(I could be wrong) is that the i860 does not have hardware pids.  In
>other words the TLB only maintains the virtual address - meaning that
>you have to flush on EACH context switch (I wouldn't have brought it
>up if there were hardware pids).  It is hard for me to believe that
>this is really the case, but that is the impression that I have gotten
>(my only information is the net and _Microprocessor Report_).

What benefit would hardware PIDs give the i860?  Hardware PIDs make
sense if you have a large cache and frequent context switches, where
it's likely that data from a process will stay in the cache long enough
so that it is still in the cache when the process is resumed, IMHE (In My
Humble Estimation).  Otherwise, the hardware PID decreases performance
slightly because you have to maintain them, and just spreads the
cache-flush and reload time over a longer period.

If you find your system spending a lot of time flushing the cache, then
try to decrease the number of context switches per second.  I think
some workstations have a higher context switch rate than is necessary
for good response.  Also, if you have a multiprocessor, you don't need
as high a switch rate.  In fact while the number of processes is
less than or equal to the number of processors, you don't need to
context switch at all.

OS people find it too easy to solve response time problems by just
turning up the context switch rate.  There are other ways to do it,
like figuring up which task that is ready to run is likely to be the
one that the user will is waiting for.  Now this doesn't mean that you
can't interrupt frequently for the purposes of, say, profiling.

You don't have to flush the i860's cache/tlb when you switch to
supervisor mode do you?  That would be pretty bad, IMHE.

	Rob Bedichek  (robertb@cs.washington.edu)

  "When the last snickerdoodle is eaten, and the last Safeway is closed,
   you will discover that you can not eat money."