Path: utzoo!attcan!uunet!lll-winken!ames!oliveb!Ricerca!lance From: lance@Ricerca.orc.olivetti.com (Lance Berc) Newsgroups: comp.arch Subject: i860 cache flushing Message-ID: <39485@oliveb.olivetti.com> Date: 19 Mar 89 02:29:52 GMT Sender: news@oliveb.olivetti.com Reply-To: lance@orc.olivetti.com (Lance Berc) Organization: Olivetti Research Center, Menlo Park, CA Lines: 35 Distribution: As has been said, the i860 has two on-chip virtual caches (4k I + 8k D) and a 64 entry TLB, all of which need to be invalidated when context switching (and sometimes when the memory map is changed). The D-cache has to be flushed as well as invalidated (code is treated as immutable - self modifying code won't work unless it lives in non-cached pages). Intel estimates that at 33MHz flushing the D-cache takes on average 30usec (30% - 50% dirty) and 60usec worst case. I believe that these numbers assume no wait-state memory (fastest possible 5 2 2 2 CPU to memory write cycles). I'd be interested in seeing some numbers on the frequency of both context switching and interrupt handling in `typical' state-of-the-art machines under some sort of well-defined load (such as compiles using local disks under Unix on Sun-3s,4s, MIPS boxes, etc). This might help determine just how important raw context switch times are. Fast context switches are important, but it seems that standard Unix time quanta are not shrinking as the amount of work done per quantum increases. So maybe the percentage of CPU time spent context switching versus the amount of time spent doing `useful' work is becoming small enough that the raw context switch time is becoming less significant. The i860 seems to favor using silicon to gain sheer straight-line speed at the expense of some performance in the curves. Sounds like a good trade off to me, but it depends on where you drive... lance lance@orc.olivetti.com (415) 496-6200 Lance Berc lance@orc.olivetti.com Beer as an alternate Olivetti Research Center lance%orc.uucp@unix.sri.com currency! Menlo Park, California (415) 496-6248 < These opinions bear no resemblance to those of Ing. C. Olivetti & C. SpA. >