Path: utzoo!attcan!uunet!tektronix!sequent!mntgfx!mbutts
From: mbutts@mntgfx.mentor.com (Mike Butts)
Newsgroups: comp.arch
Subject: Re: What kinds of problems...
Message-ID: <1989Mar18.170407.243@mntgfx.mentor.com>
Date: 19 Mar 89 01:04:05 GMT
References: <7137@phoenix.Princeton.EDU>
Distribution: na
Organization: Mentor Graphics Corporation, Beaverton Oregon
Lines: 32

From article <7137@phoenix.Princeton.EDU>, by mbkennel@phoenix.Princeton.EDU (Matthew B. Kennel):
> Are there any really big jobs out there that are seriously bounded
> by integer CPU performance?  (Excuse me, but I'm probably very naive)

One major 'black hole' for integer performance is logic and fault simulation.  A modern
event-driven logic simulator, which models the operation of a digital logic system with great 
detail (0/1/unknown, various drive strengths, gate delays which depend on logic value, spike
detection, etc., etc., not to mention behavioral models, switch-level models, etc.),
is a large, very irregular program with no floating point at all.  Lots of data-dependent
branches and pointer chasing.  Since a modern chip can have over 100K gates, and hundreds
of bytes per gate is required to store the data, tens, even hundreds of megabytes of physical 
memory is required, so things must be packed into irregular data structures.  

So far, full-functionality logic simulation has proven resistant to vectorization or any other 
kind of high-level parallelization.  Since the topology of a logic network is very irregular,
we don't get to take advantage of the beautiful regularities and predictabilities available
in scientific computing.  Hardware implementations of the algorithm have helped sometimes,
but they are notoriously inflexible and restricted to a subset of the problems.  Parallel
simulation is a subject of research, but with no major commercial impact yet.

Logic simulation is required for modern VLSI development, to have any chance at all of working
silicon in the first few tries.  Since it takes hours to simulate milliseconds on any computer 
in existence, we'll take all the integer performance we can get, thank you.  Fault simulation, 
used for developing test sequences to run on chips as they are fabricated, is worse still.

It's a challenging problem.  Give us 100 MIPS and we'll be happy for awhile, then beg for 1000.

-- 
Mike Butts, Research Engineer         KC7IT           503-626-1302
Mentor Graphics Corp., 8500 SW Creekside Place, Beaverton OR 97005
...!{sequent,tessi,apollo}!mntgfx!mbutts OR  mbutts@pdx.MENTOR.COM
These are my opinions, & not necessarily those of Mentor Graphics.