Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!cs.utexas.edu!loyola!ross!doug
From: doug@ross.UUCP (doug carmean)
Newsgroups: comp.arch
Subject: Re: Virtual caches & PIDs [was Re: i860 CPU information]
Message-ID: <227@ross.UUCP>
Date: 20 Mar 89 18:07:17 GMT
Reply-To: doug@ross.UUCP (doug carmean)
Organization: ROSS Technology. Austin, TX
Lines: 38

In article <15531@winchester.mips.COM> John Mashey writes:
...
>	Suppose you have executed process A, using that program,
>	and you context-switch to program B, using that same program.
>	You switch to the new program's PID, and even though it may
>	be executing the exact same code, it I-cache-misses on all of it,
>	because it has the wrong PID. Same thing happens for shared libraries.
>	Same thing happens if it uses shared data, which things like
>	DBMS do, or perhaps, on some systems X-clients & X-server;
>	only this time it D-cache misses.  This is especially exciting
>	for dirty data: A writes some data.  B attempts to read it.
>	Since the PID's mismatch, you flush it to memory, then you
>	re-read it to get one there with the right copy.
...
Mr. Mashey's description is entirely accurate for a system that uses
a very simple cache controller, i.e. one that does not detect aliases.  
Higher performance systems will check the physical address of the
requested virtual address against the physical address of the cache line
that is to be replaced.  If the two physical addresses match, the 
cache is used to handle the access, else the cache miss processed as
a normal miss.

In most implementations, the aliased data/instruction can be provided
with only a one cycle penalty over the cache hit access.  An implementation
might choose to overwrite the cache tag context with the new context so
that subsequent accesses will hit cache without the alias detection
penalty (assuming the context switching scenario that Mr. Mashey 
proposed).  If yet another context switch occurs, the same sequence of
operations would occur with the first access incurring the alias 
detection penalty and subsequent accesses hitting the cache.

This approach may not offer quite the performance or the glamour that
the HP PA offers, but it is considerably higher performance than the 
approach Mr. Mashey outlined.  
-- 
-doug carmean                           ross!doug@cs.utexas.edu
-ROSS Technology, 7748 Hwy 290 West Suite 400, Austin, TX 78736
-disclaimer: <insert anything you like here>