Path: utzoo!utgpu!utstat!jarvis.csri.toronto.edu!mailrus!ames!oliveb!apple!rutgers!att!westmark!mole-end!mat
From: mat@mole-end.UUCP (Mark A Terribile)
Newsgroups: comp.lang.c
Subject: Re: Contiguous Arrays
Summary: A pox on prevalidated address registers ...
Message-ID: <147@mole-end.UUCP>
Date: 11 Mar 89 05:52:57 GMT
References: <2508@ssc-vax.UUCP> <8943@alice.UUCP> <1828@valhalla.ee.rochester.edu> <7309@killer.DALLAS.TX.US>
Organization: mole-end--private system.  admin: mole-end!newtnews
Lines: 46

>  > There is no guarantee that there is a way to represent &space[0] - 101
>  > at all.  Further, computing it may cause overflows such that
>  > 	(&space[0] - 101) + 101 != &space[0]
> ... what architecture would allow [this]?
>  > ...  Even computing &space[0] - 101 could cause core dumps ...
 
> ... but I would expect a computer that does anything but return equality in
> the above expression to be broken as a mathematical engine.

Actually not.  It's broken as an addressing engine.

Some machines require pointers to be handled in special registers, or to be
composed of more than one register (Intel segmented architecture).  Address
computation is not performed by addition instructions but by loading a base
register and an index register and executing a ``load address'' or ``compute
address'' instruction.  

Unfortunately, some such architectures, in order to maintain performance
based on the way their designers assumed that the registers would be used
(I don't know if they were still studying FORTRAN execution on early
System 360s or what) force the address to be validated against limit registers
and page valid registers and so forth when one of the address registers is
loaded.  Because of the normal limitations in the ``normal'' machine models,
the Intel machines are less vulnerable than they might be, but one can easily
conceive of a machine in which addressing exceptions would be generated at the
decrement of a register.  Or in which an address register would be marked
INVALID and all future instructions ignored until the register was reloaded
from memory.

Why not use ordinary instructions and only load the address registers when you
really want to perform the indirection?  Perhaps the address space is 18 bits
or 22 bits wide and all your arithmetic instructions are limited to 8 bits
and an add-with-carry takes half-again as long as an add.  (It *shouldn't*,
but in a world where Intel can create their bizzare segmented architecture,
anything can happen.)  Perhaps the address validation on the segment register
is *sooo* costly that the compiler prefers to keep it loaded.  (Validation on
the 286 in virtual mode requires two table lookups accomplished in firmware
and takes more than 20 clock cycles.)

Such designs may be DUMB, but that doesn't stop people from thinking that
they are neat ideas.  One of these days I will read up on the 386 and see
what they had to bolix to get the large contiguous instruction space.
-- 

(This man's opinions are his own.)
From mole-end				Mark Terribile