Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!YKTVMH.BITNET!PERSHNG
From: PERSHNG@YKTVMH.BITNET ("John A. Pershing Jr.")
Newsgroups: comp.protocols.ibm
Subject: (none)
Message-ID: <8903171459.AA15321@jade.berkeley.edu>
Date: 17 Mar 89 14:37:09 GMT
Sender: daemon@ucbvax.BERKELEY.EDU
Reply-To: "John A. Pershing Jr." <PERSHNG%YKTVMH.bitnet@jade.berkeley.edu>
Organization: The Internet
Lines: 20

"Wait states" typically refer to the fact that the machine's memory
cannot supply data and/or instructions to the processor as quickly as the
processor wants them.

For instance, the processor encounters a simple LOAD instruction, so it
puts the address out onto the bus and issues a "READ" request.  The
memory is not fast enough to decode the address bits and deliver the bits
in the very next bus cycle, so the processor waits for the following bus
cycle.  If the processor is a lot faster than the memory, then it may
have to wait for two or three bus cycles before the data is delivered.

There are two general approaches to minimize and/or eliminate wait
states:  either populate the system with "fast" memory (as fast as the
processor, that is), or put a "fast" cache between the processor and the
memory such that most of the memory references will be satisfied by the
cache.  For large memory sizes, caches tend to be more cost-effective.
(The 50Z relies on fast memory, rather than a cache.)

      John Pershing
      IBM Research, Yorktown Heights