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From: elind@ircam.ircam.fr (Eric Lindemann)
Newsgroups: comp.arch,comp.sys.intel
Subject: i860 Multiprocessing
Message-ID: <494@ircam.UUCP>
Date: 13 Mar 89 10:54:10 GMT
Sender: elind@ircam.UUCP
Reply-To: elind@ircam.ircam.fr (Eric Lindemann)
Organization: l'Institut de Recherche et Coordination Acoustique-Musique
Lines: 20

I'm interested in memory access statistics (cache hit rate, external accesses
per second, etc.) for the i860 running "typical" scalar code. This is with 
an eye to evaluating it's performance in a tightly coupled, shared memory, 
multiprocessor configuration. 

Does the high speed of the i860, combined with it's smallish caches, imply
that a single processor will consume so much of the external bus bandwidth 
that trying to put four or even two i860s on a shared memory bus would
lead to  unacceptable performance degradation?

This problem is fairly easy to analyze on paper for specific vector routines
but requires more ellaborate simulation and profiling for the general
computing case. 

I'm interested here mainly in performance issues. Let's leave the issue
of cache coherency, and the lack of i860 hardware support for it, out 
of the discussion for the time being.

Eric Lindemann
IRCAM (Institute for Research and Coordination of Acoustics and Music)