Xref: utzoo comp.arch:8817 comp.sys.intel:767
Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ncar!ames!lll-winken!vette!brooks
From: brooks@vette.llnl.gov (Eugene Brooks)
Newsgroups: comp.arch,comp.sys.intel
Subject: Re: i860 Multiprocessing
Keywords: i860, MC88000, cache, coherency, multiprocessor
Message-ID: <22061@lll-winken.LLNL.GOV>
Date: 17 Mar 89 06:44:48 GMT
References: <494@ircam.UUCP> <3032@alliant.Alliant.COM> <7618@june.cs.washington.edu>
Sender: usenet@lll-winken.LLNL.GOV
Reply-To: brooks@maddog.llnl.gov (Eugene Brooks)
Followup-To: comp.arch
Organization: Lawrence Livermore National Laboratory
Lines: 12

In article <7618@june.cs.washington.edu> robertb@uw-june.UUCP (Robert Bedichek) writes:
>Build a dual-ported tag ram?  Very expensive.
>There's not such thing as free cache coherency!
If you are serious about multiprocessor performance you want a dual ported
tag ram.  On a bus based system you crank up the number of processors until
the bus can't take it anymore and therefore end up snooping the devil out of
the cache.  If you don't have dual ported tags there are no access cycles left
for the processor.  Any bus based shared memory multiprocessor worth its
salt has dual ported tags.


brooks@maddog.llnl.gov, brooks@maddog.uucp, .../uunet!maddog.llnl.gov!brooks