Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!iuvax!rutgers!apple!voder!pyramid!prls!mips!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.arch Subject: Re: Virtual caches & PIDs Message-ID: <15626@winchester.mips.COM> Date: 21 Mar 89 04:08:16 GMT References: <227@ross.UUCP> Reply-To: mash@mips.COM (John Mashey) Organization: MIPS Computer Systems, Sunnyvale, CA Lines: 27 In article <227@ross.UUCP> doug@ross.UUCP (doug carmean) writes: >In article <15531@winchester.mips.COM> John Mashey writes: >... >Mr. Mashey's description is entirely accurate for a system that uses >a very simple cache controller, i.e. one that does not detect aliases. Description of virtual-physical cache setup. .... >This approach may not offer quite the performance or the glamour that >the HP PA offers, but it is considerably higher performance than the >approach Mr. Mashey outlined. Hmmm. Maybe I wasn't clear enough in the original posting: 1) There was no intent to portray the "simple-virtual-cache-wth-pids" as particularly good. It's a tradeoff that one can make, and people build them that way, sometimes. The posting was just a description, as there had been some confusion about what these things were. NOTE: R3000s, of course, use physically-mapped caches. 2) There are all sorts of things that one can build, of course, with different cost/performance tradeoffs, to get more out of virtual caches. -- -john mashey DISCLAIMER: UUCP: {ames,decwrl,prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086