Newsgroups: comp.arch
Path: utzoo!henry
From: henry@utzoo.uucp (Henry Spencer)
Subject: Re: How to use silicon (was Re: Intel/MIPS Dhrystone ratio)
Message-ID: <1989Mar21.194914.3284@utzoo.uucp>
Organization: U of Toronto Zoology
References: <37196@bbn.COM> <1989Mar16.190043.23227@utzoo.uucp> <24889@amdcad.AMD.COM> <355@bnr-fos.UUCP>
Date: Tue, 21 Mar 89 19:49:14 GMT

In article <355@bnr-fos.UUCP> schow@bnr-public.UUCP (Stanley Chow) writes:
>With enough gates, the CPU will get more functional units, this means
>small RISC instructions will not be able to keep all the functional
>units busy....

Right, we will find things like VLIW getting more popular, assuming that
the compiler technology is up to it.  (It's not clear that Intel's is.)
However, we will *not* find dedicated adders being thrown in just for
address arithmetic -- we will find extra ALUs that *can* be used for
that but can also be used for other things.  We will not find autoincrement
addressing modes coming back, but we may find VLIWish machines that can
do the memory access and address-register increment in the same cycle,
as two separate operations independently controlled by the program.
Autoincrement addressing modes simply aren't a worthwhile investment.

>Having the H/W be tolerant of alignment means a lot of flexibility in the
>design trade-off.

It's just as easy to have the software cope with it (either directly or
via the compiler generating special code) in the rare cases where it is
needed.  This lets occasional needy software use it, *without* investing
any hardware complexity in it.

>Also, with more and more gates on a chip, it is conceivable that someone 
>will put together a cache that can handle misalignment in the cache...

Sure.  But who would *bother*?  It's just not worth it.
-- 
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