Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!rutgers!rochester!bbn!apple!vsi1!wyse!mips!prls!philabs!linus!alliant!jeff
From: jeff@Alliant.COM (Jeff Collins)
Newsgroups: comp.arch
Subject: Re: i860 CPU information
Keywords: i860 N10
Message-ID: <3040@alliant.Alliant.COM>
Date: 16 Mar 89 19:04:01 GMT
References: <1895@oakhill.UUCP> <21570@shemp.CS.UCLA.EDU> <3024@alliant.Alliant.COM> <15213@winchester.mips.COM> <706@m3.mfci.UUCP>
Reply-To: jeff@alliant.Alliant.COM (Jeff Collins)
Distribution: usa
Organization: Technology Partners, Inc.
Lines: 17

In article <706@m3.mfci.UUCP> rodman@mfci.UUCP (Paul Rodman) writes:
>In article <15213@winchester.mips.COM> mash@mips.COM (John Mashey) writes:
>>As I posted in <15016@winchester>, you have to flush the caches
>>on context-switch in a single CPU, much less a multiprocessor.
>>
>Once you've cycled around all the hardware pids, you *then* have to 
>actually flush the cache. But this is only one time in 256,1024 ,etc,etc..
>
>So, I assume this is what you guys mean when you say "flush the cache".

	Yep, that is the way most people do it, but my understanding
(I could be wrong) is that the i860 does not have hardware pids.  In
other words the TLB only maintains the virtual address - meaning that
you have to flush on EACH context switch (I wouldn't have brought it
up if there were hardware pids).  It is hard for me to believe that
this is really the case, but that is the impression that I have gotten
(my only information is the net and _Microprocessor Report_).