Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!rutgers!rochester!bbn!apple!vsi1!wyse!mips!prls!philabs!linus!alliant!jeff
From: jeff@Alliant.COM (Jeff Collins)
Newsgroups: comp.arch
Subject: Re: i860 CPU information
Keywords: i860 N10
Message-ID: <3041@alliant.Alliant.COM>
Date: 16 Mar 89 19:19:24 GMT
References: <1895@oakhill.UUCP> <21570@shemp.CS.UCLA.EDU> <3024@alliant.Alliant.COM> <21784@shemp.CS.UCLA.EDU>
Reply-To: jeff@alliant.Alliant.COM (Jeff Collins)
Distribution: usa
Organization: Alliant Computer Systems, Littleton, MA
Lines: 39

In article <21784@shemp.CS.UCLA.EDU> marc@cs.ucla.edu (Marc Tremblay) writes:
>In article <3024@alliant.Alliant.COM> jeff@alliant.Alliant.COM (Jeff Collins) writes:
>>In article <21570@shemp.CS.UCLA.EDU> marc@cs.ucla.edu (Marc Tremblay) writes:
>>:Invalidating cache lines externally is not an absolute requirement for 
>>:using caches in a multi-processor environment. 
>>
>>	Which policies are these?  How does one share memory in a
>>	multiprocessor when you can't have external bus watchers?
>
>1) As mentioned in another article making sharable pages uncachable
>   can be a viable answer for various configurations. Remember not
>   everything is bus-based, (i.g. interconnection networks),
>   so a broadcasts may not be allowed.
>

	You are right.  My bias for shared memory, symmetric, bus-based,
multiprocessors with snoopy caches is so strong that I forget about
interconnection networks.

>2) Directory-based cache coherency scheme: several papers have been
>   published about this method. One of them is:
>
>Bus watchers are nice but are not an absolute necessity for
>implementing efficient multiprocessor systems.

	Actually I know how directory based cache coherency works, but you
still need the ability to invalidate the internal cache from external logic.
The memory will detect that a cache location on a processor needs to be
invalidated and send an invalidate signal (with the physical address) to
the CPU card.  The CPU card must then (because the internal cache is virtual)
do a reverse TLB lookup and then signal the internal cache to invalidate.  All
of this works just fine with two exceptions on the i860.  1). it is not
possible to do the reverse TLB look up (not enough information external to the
processor) and 2). there is no way to send the invalidate (even if you could
figure out the correct virtual address to invalidate).

	I stand by my claim.  There is no way to put this processor into a
shared memory, bus-based, symmetric multiprocessor unless you disable the
D-cache or make all software that might share data manage the D-cache.