Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!lll-winken!uunet!microsoft!w-colinp
From: w-colinp@microsoft.UUCP (Colin Plumb)
Newsgroups: comp.arch
Subject: Re: Intel/MIPS Dhrystone ratio
Message-ID: <12@microsoft.UUCP>
Date: 21 Mar 89 06:10:56 GMT
References: <1552@vicom.COM> <15690@cup.portal.com> <1562@vicom.COM> <37196@bbn.COM> <1989Mar16.190043.23227@utzoo.uucp> <24889@amdcad.AMD.COM>
Reply-To: w-colinp@microsoft.uucp (Colin Plumb)
Organization: very little
Lines: 20

tim@amd.com (Tim Olson) wrote:
> Also, auto-incrementing addressing modes imply:
> 
> 	- Another adder (to increment the address register in parallel)
> 	- Another writeback port to the register file

Another adder?  Most RISC chips use base+offset addressing; all you need is
the ability to send the result back to the base register as well as to
the address bus.  This is almost always possible for stores, and may be
possible for loads, since the result of the load generally comes in
significantly later then the address goes out.  (The 29000 uses this cycle
to store back the result of the previous load, which had been waiting in a 
scoreboard register, but other schemes may do something else.)

In my dream chip, I added postincrement by latching the address from the ALU
input bus, and was happy.
-- 
	-Colin (uunet!microsoft!w-colinp)

"Don't listen to me.  I never do." - The Doctor