Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!lll-winken!uunet!microsoft!w-colinp
From: w-colinp@microsoft.UUCP (Colin Plumb)
Newsgroups: comp.arch
Subject: Re: How to use silicon (was Re: Intel/MIPS Dhrystone ratio)
Message-ID: <13@microsoft.UUCP>
Date: 21 Mar 89 06:54:04 GMT
References: <37196@bbn.COM> <1989Mar16.190043.23227@utzoo.uucp> <24889@amdcad.AMD.COM> <355@bnr-fos.UUCP>
Reply-To: w-colinp@microsoft.uucp (Colin Plumb)
Organization: very little
Lines: 30

schow@bnr-public.UUCP (Stanley Chow) wrote:
> [A lot of things about addressing modes I agree with]

> Even now, there are real money issues in memory alignments. If you have
> a system with a 100 MegaBytes main memory and "correct" alignment makes 
> it 150 MB, you have just made the system 50% more expensive. Or how about
> alignment bumps your memory requirement from 63K to 65K causing extra chips
> and possible board layout problems (not to mention the cost)?
> 
> Having the H/W be tolerant of alignment means a lot of flexibility in the
> design trade-off.

And a lot of headaches in the cache miss and page fault recovery departments.

In any structure, if you rearrange the components, you can lose at most
n-1 bytes to padding, where n is the strictest alignment restriction.  For
most processors, the worst case is a double and a char, 7 bytes out of 16
wasted.  But if this is a major concern, rewrite the code to use two parallel
arrays.  You'll waste at most 7 bytes total (in your 100Meg).

In C, this is a bit of a bother, but not too bad.  I think requiring alignment
is one thing that'll never go out of style.  On any chip, you want to do it
because it's more efficient, anyway.  The only need for unaligned accesses is
to handle old data formats, which presumably need old programs run on them,
which will (except in pathological cases) run faster on the new machine
anyway.
-- 
	-Colin (uunet!microsoft!w-colinp)

"Don't listen to me.  I never do." - The Doctor