Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!lll-winken!uunet!microsoft!w-colinp
From: w-colinp@microsoft.UUCP (Colin Plumb)
Newsgroups: comp.arch
Subject: Re: i860 CPU information
Message-ID: <14@microsoft.UUCP>
Date: 21 Mar 89 07:00:18 GMT
References: <1895@oakhill.UUCP> <21570@shemp.CS.UCLA.EDU> <3024@alliant.Alliant.COM> <15213@winchester.mips.COM> <706@m3.mfci.UUCP> <3040@alliant.Alliant.COM>
Reply-To: w-colinp@microsoft.uucp (Colin Plumb)
Distribution: usa
Organization: very little
Lines: 22

jeff@alliant.Alliant.COM (Jeff Collins) wrote:
> 	Yep, that is the way most people do it, but my understanding
> (I could be wrong) is that the i860 does not have hardware pids.  In
> other words the TLB only maintains the virtual address - meaning that
> you have to flush on EACH context switch (I wouldn't have brought it
> up if there were hardware pids).  It is hard for me to believe that
> this is really the case, but that is the impression that I have gotten
> (my only information is the net and _Microprocessor Report_).

This is the case.  You have to flush the cache every context switch.
(Since it's a write-back cache, you have to at least flush the pending
writes before messing with the page table, anyway.)  

For those interested, as far as I can tell, the i860's flush instruction
is half a load, that forces the write-back (you play with bits in a
status register to force a given set ito be used) but loads a bogus value
into the cache and the destination register.  I don't think the cache has
valid bits.
-- 
	-Colin (uunet!microsoft!w-colinp)

"Don't listen to me.  I never do." - The Doctor