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From: tim@crackle.amd.com (Tim Olson)
Newsgroups: comp.arch
Subject: Autoincrement [was Re: Intel/MIPS Dhrystone ratio]
Message-ID: <24935@amdcad.AMD.COM>
Date: 21 Mar 89 17:45:32 GMT
References: <1552@vicom.COM> <15690@cup.portal.com> <1562@vicom.COM> <37196@bbn.COM> <1989Mar16.190043.23227@utzoo.uucp> <24889@amdcad.AMD.COM> <12@microsoft.UUCP>
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Reply-To: tim@amd.com (Tim Olson)
Organization: Advanced Micro Devices, Inc. Sunnyvale CA
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In article <12@microsoft.UUCP> w-colinp@microsoft.uucp (Colin Plumb) writes:
| tim@amd.com (Tim Olson) wrote:
| > Also, auto-incrementing addressing modes imply:
| > 
| > 	- Another adder (to increment the address register in parallel)
| > 	- Another writeback port to the register file
| 
| Another adder?  Most RISC chips use base+offset addressing; all you need is
| the ability to send the result back to the base register as well as to
| the address bus.

I must have had my architectural blinders on that day -- others have
pointed this out to me as well.

I was thinking about the other adder requirement because the offset is
typically used to supply a constant offset from the current "frame
pointer" [be it an actual register or an adjustment from the stack
pointer] for local array accesses.  However, this need not be the case
-- it can be folded in to the base register at the top of the loop (like
the Am29000 does) and the offset field can be used as the increment
specifier.


	-- Tim Olson
	Advanced Micro Devices
	(tim@amd.com)