Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cornell!uw-beaver!tektronix!tekecs!frip!andrew
From: andrew@frip.wv.tek.com (Andrew Klossner)
Newsgroups: comp.arch
Subject: Re: i860 CPU information
Message-ID: <11170@tekecs.GWD.TEK.COM>
Date: 21 Mar 89 23:02:40 GMT
References: <1895@oakhill.UUCP> <21570@shemp.CS.UCLA.EDU>
Sender: andrew@tekecs.GWD.TEK.COM
Distribution: usa
Organization: Tektronix, Wilsonville, Oregon
Lines: 23

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		"Still on the subject of the caches:  There is no way
		to externally invalidate cache lines.  This makes the
		part virtually unusable in multi-processing
		configurations, since cache coherency cannot be
		maintained."

	"Invalidating cache lines externally is not an absolute
	requirement for using caches in a multi-processor environment.
	There are policies that do not require this feature at all."

Furthermore, you can achieve the necessary effect by sending the other
CPU a message telling it to invalidate its cache lines.  If exception
handling (get in, do it, get out) is fast enough, and if you don't do
this every few nanoseconds, then the performance degradation shouldn't
be a big deal.

You don't absolutely need an external invalidation signal in hardware
for multiprocesisng.

  -=- Andrew Klossner   (uunet!tektronix!orca!frip!andrew)      [UUCP]
                        (andrew%frip.wv.tek.com@relay.cs.net)   [ARPA]