Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!nrl-cmf!ames!oliveb!apple!voder!pyramid!prls!philabs!linus!alliant!jeff
From: jeff@Alliant.COM (Jeff Collins)
Newsgroups: comp.arch
Subject: Re: i860 CPU information
Keywords: i860 N10
Message-ID: <3047@alliant.Alliant.COM>
Date: 20 Mar 89 15:38:52 GMT
References: <1895@oakhill.UUCP> <21570@shemp.CS.UCLA.EDU> <3024@alliant.Alliant.COM> <15213@winchester.mips.COM> <706@m3.mfci.UUCP> <3040@alliant.Alliant.COM> <7630@june.cs.washington.edu>
Reply-To: jeff@alliant.Alliant.COM (Jeff Collins)
Organization: Technology Partners, Inc.
Lines: 29

In article <7630@june.cs.washington.edu> robertb@uw-june.UUCP (Robert Bedichek) writes:
>In article <3040@alliant.Alliant.COM> 
>  jeff@alliant.Alliant.COM (Jeff Collins) writes:
>>	Yep, that is the way most people do it, but my understanding
>>(I could be wrong) is that the i860 does not have hardware pids. 
>
>What benefit would hardware PIDs give the i860?  Hardware PIDs make
>sense if you have a large cache and frequent context switches, where
>it's likely that data from a process will stay in the cache long enough
>so that it is still in the cache when the process is resumed, IMHE (In My
>Humble Estimation).  Otherwise, the hardware PID decreases performance
>slightly because you have to maintain them, and just spreads the
>cache-flush and reload time over a longer period.
>
> <comments on increasing context switch time deleted>
>

	It is true that an 8k data cache is fairly small, and hardware
PIDs for a cache of that size may not be a win - all my mail was
attempting to say, however, was that the cache must be flushed at each
context switch.  I, personally, am not a fan of caches that must be
flushed at each context switch - this is independent of the rate of
context switches (having to flush the caches will always be slower
than not having to flush them).  Yes, you can decrease the average cost
of the cache flush by having longer times between context switches.

	The real objection is more from an architectural point of view:
what happens if/when Intel increases the size of the D-cache?  Will
they then add hardware PIDs?