Path: utzoo!attcan!uunet!lll-winken!xanth!ames!ames.arc.nasa.gov!lamaster
From: lamaster@ames.arc.nasa.gov (Hugh LaMaster)
Newsgroups: comp.arch
Subject: Re: RISC as a "technology window"?
Message-ID: <22987@ames.arc.nasa.gov>
Date: 23 Mar 89 02:30:18 GMT
References: <1552@vicom.COM> <15690@cup.portal.com> <1562@vicom.COM> <15702@clover.ICO.ISC.COM> <27681@apple.Apple.COM> <15695@winchester.mips.COM> <22974@ames.arc.nasa.gov>
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In article <22974@ames.arc.nasa.gov> lamaster@ames.arc.nasa.gov (Hugh LaMaster) writes:

>
> (About some of his favorite topics.)
>

Of course the Motorola 88K
does essentially what I asked, although the cache setup is slightly different.
They don't have AS MUCH FPU hardware as was being talked about in what I was
responding to, but conceptually, they are already doing it, so my point was
confused.  The Clipper also.  My point was to explore which designs minimize
the off-chip bandwidth required, and why, in the context of 1M+ transistor
chips, assuming that high performance arithmetic is a given. 

  Hugh LaMaster, m/s 233-9,  UUCP ames!lamaster
  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
  Moffett Field, CA 94035     
  Phone:  (415)694-6117