Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ukma!xanth!lll-winken!uunet!portal!cup.portal.com!bcase
From: bcase@cup.portal.com (Brian bcase Case)
Newsgroups: comp.arch
Subject: Re: How to use silicon (was Re: Intel/MIPS Dhrystone ratio)
Message-ID: <16119@cup.portal.com>
Date: 22 Mar 89 22:12:50 GMT
References: <37196@bbn.COM> <1989Mar16.190043.23227@utzoo.uucp> <24889@amdcad.AMD.COM> <355@bnr-fos.UUCP> <16058@cup.portal.com> <2163@wyse.wyse.com>
Organization: The Portal System (TM)
Lines: 16

>>It just doesn't make sense to bundle,
>>bind is a better word, many operations into one instruction.  Doing so
>>simply thwarts compiler optimization.  Adresssing modes are probably the
>>worst form of semantic binding, in my opinion.
>
>If anything, VLIW is more RISCy than RISC in the sense that it exposes
>all of the functional units' pipelines to the compiler.  You just can't
>say VLIW in the same sentence with "simply thwarts compiler optimization."

I didn't!!!!  I'm sorry if there was some confusion.  My reply, from which
the above quote is taken, was to a plea for auto-increment.  I would
certainly never say that VLIW thwarts compiler optimization.  I'm sorry
if you misunderstood, but I was not knocking "semantic bundling" in the
context of VLIW, but in the context of complex addressing modes and the
like.  VLIWs are sorta like super scalars, and for that similarity, I
like them.