Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!lll-winken!ames!oliveb!pyramid!prls!philabs!linus!alliant!jeff
From: jeff@Alliant.COM (Jeff Collins)
Newsgroups: comp.arch
Subject: Re: i860 CPU information
Keywords: i860 N10
Message-ID: <3051@alliant.Alliant.COM>
Date: 21 Mar 89 15:23:14 GMT
References: <1895@oakhill.UUCP> <21570@shemp.CS.UCLA.EDU> <3024@alliant.Alliant.COM> <21784@shemp.CS.UCLA.EDU> <3041@alliant.Alliant.COM> <21972@shemp.CS.UCLA.EDU>
Reply-To: jeff@alliant.Alliant.COM (Jeff Collins)
Distribution: usa
Organization: Technology Partners, Inc.
Lines: 25

In article <21972@shemp.CS.UCLA.EDU> marc@cs.ucla.edu (Marc Tremblay) writes:
>Using a directory based cache coherency method with processors that do not
>have the capability to have their internal cache entries invalidated externally,
>the memory controller has to send a vector interrupt to one of the 
>the processors which can then invalidate the correct cache line.
>I don't know how much flexibility the "flush" instruction of the i860 offers 
>(the data sheet does not say much), but it should be possible to do it,
>if not, then too bad :-) .

	Good point.  But still all that the memory can do is send the
physical address to invalidate (it is all that it knows), this still
means that the interrupt handler has to perform a reverse translation
from physical to virtual (after determining which virtual space to
use - actually I quess the current virtual space is all that needs to
be looked at - as the D-cache must have been flushed at the last
context switch), and only then it can flush the appropriate tage line.
(I infer (from the fact that a complete D-cache flush is a loop) that
it is possible to flush particular line from the D-cache.)  Doing this
conversion is possible, but I think the conversion involves an
exhaustive search of the processes page table (this can probably be
optimized).  Oh, by the way, while you are doing the vectored
interrupt, the reverse translation and the invalidate, don't you have
to hold off the memory request that initiated this whole process (the
memory has to wait until the flush or invalidate happen before it can
reply)?  Can you say memory latency?