Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!lll-winken!uunet!steinmetz!davidsen
From: davidsen@steinmetz.ge.com (Wm. E. Davidsen Jr)
Newsgroups: comp.arch
Subject: Re: RISC as a "technology window"?
Message-ID: <13404@steinmetz.ge.com>
Date: 23 Mar 89 16:25:08 GMT
References: <1552@vicom.COM> <15690@cup.portal.com> <1562@vicom.COM> <15702@clover.ICO.ISC.COM> <27681@apple.Apple.COM> <15695@winchester.mips.COM> <22974@ames.arc.nasa.gov>
Reply-To: davidsen@crdos1.UUCP (bill davidsen)
Organization: General Electric CRD, Schenectady, NY
Lines: 43


  It's getting harder to tell RISC from CISC in some cases. If a
computer has one instruction to do something like:
	*(++a) = (*b)++
I would feel that it it is CISC. If it executes that instruction in one
cycle and doesn't use microcode, I would find it hard to argue that it
is not RISC. Processors like the N10 are approaching 1 op/cycle, and the
i80486 is rumored to have an average of < 2 for non-F.P. operations.

  I believe that people are taking RISC as a personal issue in some
cases, rather than a method of getting real work (ie. that done by the
people who pay for the computer or on their behalf) in less time and/or
for less money. If the processor becomes so fast that it requires memory
bandwidth which is unachievable or unaffordable then the true speed of
the processor is reduced by the wait states introduced. I think that in
the next five years we will see processors which outrun off chip memory,
and certainly now there are a lot of processors running at less than
full speed due to the cost of fast memory.

  There will continue to be a demand for processors with a very high
instruction rate (call them RISC if you will), and also for processors
which will perform a given task faster with limited memory bandwidth.
Vendors will continue to pick the complexity which they feel provides
the greatest cost effectiveness for the entire product based on the CPU.
Cycles per operation will come down for all vendors, because they have
the techniques to use that approach.

  I also think that vendors who are now regarded as RISC vendors will
add complexity to their instruction sets, providing (1) it doesn't slow
the chip on other operations, (2) it doesn't take real estate which
could be used for things which would improve overall performance more,
and (3) that the benefit in code size and performance (due to fewer
instructions) would be readily measurable.
________________________________________________________________

The ultimate RISC machine: a one bit opcode; 0 = conditional branch, 1 =
nop to fill the delay slots ;-)


-- 
	bill davidsen		(wedu@crd.GE.COM)
  {uunet | philabs}!steinmetz!crdos1!davidsen
"Stupidity, like virtue, is its own reward" -me