Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!rutgers!bellcore!texbell!uhnix1!sugar!ficc!cliff
From: cliff@ficc.uu.net (cliff click)
Newsgroups: comp.arch
Subject: Re: EXACTLY what is Superscalar?
Summary: Forth chips, RISC, Superscaler
Message-ID: <3529@ficc.uu.net>
Date: 23 Mar 89 15:58:37 GMT
References: <37196@bbn.COM> <1989Mar16.190043.23227@utzoo.uucp> <22975@ames.arc.nasa.gov>
Organization: Ferranti International Controls
Lines: 40

[This is my first posting, so please go easy on the flames! :-)]

> For quite a while, I have heard superscalar used, and I think the term was
> defined in a paper in IEEE Computer a while back, but I am still a little
> fuzzy on it.  Is "superscalar" an exact concept, or is it a buzzword like 
> "RISC"?  Is a Multiflw machine a superscalar machine, or the i860, or
> the Weitek XL-8064?

The NOVIX 4000 chip has 2 stacks in external memory; all operations 
implicitly used the top-of-stack (or next-of-stack) with no real 
registers.  Calls/branchs take 1 cycle, subroutine returns take ZERO 
cycles, memory loads and stores take 2 cycles (1 for instruction, 1 
for mem ref), arithmetic took 1 cycle.  The arithmetic instructions 
were explicitly bit-coded - bits in the instruction ran directly into 
the ALU/stacks - so a single instruction could choose one of 
(add/sub/neg/xor/or/and/...) and (shift left/shift right/rotate...) 
and (push results/pop results/...).  The chip had no pipeline and no 
cache.  Interrupts had a 2 cycle latency (recognize interrupt, push 
PC).  The chip was running at 10Mhz with nearly 10MIPS (no flames 
please) throughput.  Oh yeah, both stacks and main memory all had 
SEPERATE address and data lines, and it was a 16bit chip (2 x 8 stack 
address, 16 main address, 3 x 16 data lines = 80 address+data lines).

Is this (basically) register-less chip RISC?

Is this (basically) instructions-as-horizontal-microcode "Superscaler"?

Why isn't this approach more popular?  With no pipeline and no cache
context switches should be cheap (stacks swapped by using MMU).  The
builder didn't use any fancy technology for the part - the MUCH smaller
processes used by the "big boys" (Motorola, Intel, HP...) should be
able to double or triple the clock rate on the part.

(All of the NOVIX stuff is from my head and is a couple of years old, I
may have forgotten some of it!  I know that a 32bit part is in the works.)


Cliff Click, Xenix Support, Ferranti International Controls Corporation.
uunet.uu.net!ficc!cliff, cliff@ficc.uu.net, +1 713 274 5368.
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