Path: utzoo!utgpu!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!ucbvax!amdcad!rpw3
From: rpw3@amdcad.AMD.COM (Rob Warnock)
Newsgroups: comp.arch
Subject: Re: i860 cache flushing
Message-ID: <24958@amdcad.AMD.COM>
Date: 23 Mar 89 05:08:09 GMT
References: <39485@oliveb.olivetti.com>
Reply-To: rpw3@amdcad.UUCP (Rob Warnock)
Organization: [Consultant] San Mateo, CA
Lines: 28

In article <39485@oliveb.olivetti.com> (Lance Berc) writes:
+---------------
| Intel estimates that at 33MHz flushing the D-cache takes on average
| 30usec (30% - 50% dirty) and 60usec worst case. I believe that these
| numbers assume no wait-state memory (fastest possible 5 2 2 2 CPU to
+---------------

Similarly, because of the very large register file, the Am29000 appears
at first to have a problem with full context switching (*not* system calls
or interrupts, those continue the stack-cache discipline), since you have
to save/restore 160 of the 192 registers (if 32 are reserved to the kernel).
But at 25 MHz, using the load/store-multiple instructions and burst-mode
memories (using normal static-column DRAMs bank-interleaved 2:1, still cheap),
you can save the old user's full register set and load up the new user's
full set in 12.8 microseconds. [The TLB has PIDs, so no flush there.]

I just don't see 20-50 VUPS type of systems needing to do tens of thousands
of full context switches per second, at least not in general-purpose
timesharing...


Rob Warnock
Systems Architecture Consultant

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