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From: tim@crackle.amd.com (Tim Olson)
Newsgroups: comp.arch
Subject: Re: physical vs. virtual cache
Message-ID: <24974@amdcad.AMD.COM>
Date: 24 Mar 89 17:15:23 GMT
References: <13413@steinmetz.ge.com>
Sender: news@amdcad.AMD.COM
Reply-To: tim@amd.com (Tim Olson)
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Organization: Advanced Micro Devices, Inc. Sunnyvale CA
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In article <13413@steinmetz.ge.com> davidsen@crdos1.UUCP (bill davidsen) writes:
| Would someone like to describe the less obvious features of cache types
| in terms of real estate, design problems, etc? I see lots of allusions
| but damn few hard facts.
| 
| Unless you disagree with these, they've been mentioned many times:
| 	virtual:
| 	  fast, no address translation needed
| 	physical:
| 	  no need to flush on context switch
| 	  no aliasing problems

Also add:
	physical:
	  easier to design in multiprocessing features, such as
	  bus-snooping & ownership; virtual caches may require reverse
	  translation maps.

	  can be accessed in parallel with MMU translation if cache-line
	  indecies are taken from the untranslated address bits (I
	  believe the 88200 does this).  This can allow physical caches
	  to be as fast as virtual.


	-- Tim Olson
	Advanced Micro Devices
	(tim@amd.com)